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true 18 - bit, voltage output dac 0.5 lsb inl, 0.5 lsb dnl data sheet ad5781 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their res pective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2010 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features single 18 - bit dac, 0.5 lsb inl 7.5 nv/hz n oise s pectral d ensity 0.05 lsb l ong - t erm l inearity s tability < 0.05 ppm/c t emperature d rift 1 s s ettling t ime 1 .4 nv - s ec glitch impulse operating temperature range: ? 40c to + 125c 20- l ead tssop p ackage wide p ower s upply range of up to 16.5 v 35 mhz schmitt triggered d igital i nterface 1.8 v compatible digital interface applications medical i nstrumentation test and m easurement industrial c ontrol scientific and a erospace i nstrumentation data a cquisition s ystems digital g ain and o ffset a djustment power s upply c ontrol functional block dia gram a1 6.8k? 6k? 6.8k? r1 r fb 18-bit dac dac reg 18 18 input shift register and contro l logic power-on-reset and clear logic ad5781 iov cc sdin v cc v dd v refpf v refps v refnf agnd v ss dgnd v refns sclk sync sdo ldac clr reset r fb inv v out 09092-001 figure 1. table 1 . complementary devices part no. description ad8675 ultra p recision, 36 v, 2.8 nv/hz r ail -to - r ail o utput o p a mp ad8676 ultra p recision, 36 v, 2.8 nv/hz d ual r ail - to - r ail o utput o p a mp ada4898 -1 high v oltage, l ow n oise, l ow d istortion, u nity g ain s table, h igh s peed o p a mp table 2 . related devices part no. description ad5791 20-b it, 1 ppm accurate dac ad5541a / ad5542a 16-b it, 1 lsb a ccurate 5 v dac general description the ad5781 1 is a si ngle 18 - bit, unbuffered voltage output dac that operates from a bipo lar supply of up to 33 v. t h e ad5781 accepts a positive reference input range of 5 v to v dd ? 2.5 v and a negative reference input range of v ss + 2.5 v to 0 v. t h e a d5781 offers a relative accuracy specification of 0.5 lsb max imum , and operation is guaranteed monotonic with a 0.5 lsb dnl max imum specification. the part uses a versatile 3 - wire serial interface that operates at clock rates of up to 35 mhz and i s com patible with standard spi , qspi?, microwire?, and dsp interface standards. the part incorporates a power - on reset circuit that ensures that the dac output powers up to 0 v and in a known output impedance state and remains in this state until a valid write to the device takes place. the part provides an output clamp feature that places the output in a defined load state. product highlights 1. true 18 - b it a ccuracy . 2. wide power supply range of up t o 16.5 v . 3. ? 40c to + 125c o perating t emperature r ange . 4. low 7.5 nv /hz n oise . 5. low 0.05 ppm/c t emperature d rift . 1 protected by u.s. patent no 7884747, and other patents are pending.
ad5781 data sheet rev . d | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function description .............................. 8 typical performance characteristics ............................................. 9 terminology .................................................................................... 17 theory of operation ...................................................................... 19 dac architecture ....................................................................... 19 hardware control pins .............................................................. 20 on - chip registers ...................................................................... 21 ad5781 features ............................................................................ 24 power - on to 0 v ......................................................................... 24 configuring the ad5781 .......................................................... 24 dac output state ...................................................................... 24 linearity compensation ............................................................ 24 output amplifier configuration .............................................. 24 applications information .............................................................. 26 typical op erating circuit ......................................................... 26 evaluation board ........................................................................ 26 outline dimensions ....................................................................... 27 ord ering guide .......................................................................... 27 revision history 7 /1 3 rev. c to rev. d changes to t 1 test conditions/comments and endnote 2 ......... 5 deleted figure 4 ................................................................................ 7 deleted daisy - chain operation section ..................................... 20 11/11 rev. b to rev. c added figure 48; renumbered s equentially .............................. 17 change to ideal transfer function equation .............................. 22 9/11 rev. a to rev. b added patent note ........................................................................... 1 changes to table 3 ............................................................................ 3 changes to opgnd description, table 12 ................................ 23 8 /11 rev. 0 to rev. a change to features section .............................................................. 1 changes to specifications section ................................................... 3 del eted t 14 parameter from timing specifications section, table 4 ................................................................................................. 5 changes to figure 2 and figure 3 .................................................... 6 changes to figure 4 ........................................................................... 7 replaced figure 42 and figure 43 ................................................ 16 added new figure 44, figure 45, and figure 46, renumbered sequentially ..................................................................................... 16 7/10 revision 0 : initia l version
data sheet ad5781 rev. d | page 3 of 28 specifications v dd = + 12.5 v to + 16.5 v, v ss = ? 16.5 v to ? 12.5 v, v refp = + 10 v, v refn = ? 10 v, v cc = + 2.7 v to + 5.5 v, i o v cc = + 1.71 v to + 5.5 v, r l = unloaded, c l = unloaded, t min to t max , unless otherwise noted. table 3 . a, b version 1 parameter min typ max unit test conditions/comments static performance 2 resolution 18 bits integral nonl inearity error (relative accuracy) ? 0.5 0.25 + 0.5 lsb b v ersion, v refp = +10 v, v refn = ? 10 v ? 0.5 0.25 + 0.5 ls b b v ersion, v refp = +10 v, v refn = 0 v 3 ? 1 0.5 + 1 lsb b v ersion, v refp = +5 v, v refn = 0 v 3 ? 4 2 + 4 lsb a v ersion 4 differential nonlinearity error ? 0.5 0.25 + 0.5 lsb v refp = +10 v, v refn = ? 10 v ? 0.5 0.25 + 0.5 lsb v refp = +10 v, v refn = 0 v 3 ? 1 0.5 + 1 lsb v refp = +5 v, v refn = 0 v 3 linearity error long - term stability 5 0.04 lsb after 500 hours at t a = 125c 0.05 lsb after 1000 hours at t a = 125c 0.03 lsb after 1000 hours t t a = 100c full - scale error ? 1.75 0.25 + 1.75 lsb v refp = +10 v, v refn = ? 10 v 3 ? 2.7 5 0. 062 + 2 . 7 5 lsb v refp = +10 v, v refn = 0 v 3 ? 5 .25 0.2 + 5 .25 lsb v refp = +5 v, v refn = 0 v 3 ? 1 0.25 +1 lsb v refp = +10 v, v refn = ?10 v 3 , t a = 0c to 105c ? 1 0.062 +1 lsb v refp = 10 v, v refn = 0 v 3 , t a = 0c to 105c ? 1.5 0.2 +1.5 lsb v refp = 5 v, v refn = 0 v 3 , t a = 0c to 105c full - scale error temperature coefficient 3 0.02 ppm fsr/c zero - scale error ? 1. 7 5 0. 025 + 1. 7 5 lsb v refp = +10 v, v refn = ? 10 v 3 ? 2.5 0.38 + 2.5 lsb v refp = +10 v, v refn = 0 v 3 ? 5 .25 0. 19 + 5 .25 lsb v refp = +5 v, v refn = 0 v 3 ? 1 0.025 +1 lsb v refp = +10 v, v refn = ?10 v 3 , t a = 0c to 105c ? 1 0.38 +1 lsb v refp = 10 v, v refn = 0 v 3 , t a = 0c to 105c ? 1.5 0.19 +1.5 lsb v re fp = 5 v, v refn = 0 v 3 , t a = 0c to 105c zero - scale error temperature coefficient 3 0.04 ppm fsr/c gain error ? 6 0.3 + 6 ppm fsr v refp = +10 v, v refn = ? 10 v 3 ? 10 0.4 + 10 ppm fsr v refp = +10 v, v refn = 0 v 3 ? 20 0.4 + 20 ppm fsr v refp = +5 v, v refn = 0 v 3 gain error temperature coefficient 3 0.04 ppm fsr/c r1, r fb matching 0.01 % output characteristics 3 output voltage range v refn v refp v output slew rate 50 v/s unbuffered output, 10 m ? ||20 pf l oad output voltage sett ling time 1 s 10 v step to 0.02%, using ad845 b uffer in unity - gain mode 1 s 125 code step to 1 lsb 6 output noise spectral density 7.5 nv/hz at 1 khz, dac code = midscale 7.5 nv/hz at 10 khz, d ac code = midscale 7.5 nv/hz at 100 khz, dac code = midscale output voltage noise 1.1 v p -p dac code = midscale, 0.1 hz to 10 hz bandwidth 7
ad5781 data sheet rev . d | page 4 of 28 a, b version 1 parameter min typ max unit test conditions/comments midscale glitch impulse 3.1 nv - sec v refp = +10 v, v refn = ? 10 v 1.7 nv - sec v refp = +10 v, v refn = 0 v 1 .4 nv - sec v refp = +5 v, v refn = 0 v msb segment glitch impulse 6 9.1 nv - sec v refp = +10 v, v refn = ?10 v, see figure 42 3.6 nv - sec v refp = 10 v, v refn = 0 v, see figure 43 1.9 nv - sec v refp = 5 v, v refn = 0 v, see figure 44 output enabled glitch impulse 45 nv - sec on removal of output ground clamp digital feedthroug h 0.4 nv - sec dc output impedance (normal mode) 3.4 k? dc output impedance (output clamped to ground) 6 k? spurious free dynamic range 100 db 1 khz tone, 10 khz sample rate total harmonic distortion 97 db 1 khz tone, 10 khz sample rate reference inputs 3 v re fp input range 5 v dd ? 2.5 v v v refn input range v ss + 2.5 v 0 dc input impedance 5 6.6 k? v refp , v refn , c ode d ependent , t ypica l at mid scale code input capacitance 15 pf v refp , v refn logic inputs 3 input c urrent 8 ? 1 + 1 a input low voltage, v il 0.3 iov cc v iov cc = 1. 71 v to 5.5 v input high voltage, v ih 0.7 iov cc v iov cc = 1. 71 v to 5.5 v pin capacitance 5 pf logic output (sdo) 3 outpu t low voltage , v ol 0.4 v iov cc = 1. 71 v to 5.5 v, sinking 1 ma output high voltage , v oh iov cc ? 0.5 v iov cc = 1. 71 v to 5.5 v, sourcing 1 ma high impedance leakage current 1 a high impedance output capacitance 3 pf power requirements a ll digital inputs at dgnd or iov cc v dd 7.5 v ss + 33 v v ss v dd ? 33 ? 2.5 v v cc 2.7 5.5 v iov cc 1.71 5.5 v iov cc v cc i dd 4.2 5.2 ma i ss 4 4.9 ma i cc 6 00 9 00 a ioi cc 52 140 a sdo disabled dc power supply rejection ratio 3 , 9 0.6 v/v v dd 10%, v ss = 15 v 0.6 v/v v ss 10%, v dd = 15 v ac power supply rejection ratio 3 95 db v dd 200 mv, 50 hz/60 hz, v ss = ? 15 v 95 db v ss 200 mv, 50 hz/6 0 hz, v dd = 15 v 1 temperature range: ?40c to +125c, typical conditions: t a = 25c, v dd = +15 v, v ss = ?15 v, v refp = +10 v, v refn = ?10 v. 2 performance characterized with ad8676 brz voltage reference buffers and ad8675 arz output buffer. 3 linearity error refers to both inl error and dnl error; either parameter can be expected to drift by the amount specified aft er the length of time specified. 4 valid for all voltage reference span s. 5 guaranteed by design and characterization, not production tested. 6 the ad5781 is configured in the bias compensation mode with a low - pass rc filter on the output. r = 300 ?, c = 143 pf (total capacitance seen by the output buffer, lead capacitance, and so forth). 7 includes noise contribution from ad8676 brz voltage reference buffers. 8 current flowing in an individual logic pin. 9 includes psrr of ad8676 brz voltage reference buffers.
data sheet ad5781 rev. d | page 5 of 28 timing characteristi cs v cc = 2.7 v to 5.5 v; all specifications t min to t max , unless otherwise noted. table 4 . parameter limit 1 unit test conditions/comments iov cc = 1.71 v to 3.3 v iov cc = 3.3 v to 5.5 v t 1 2 40 28 ns min sclk cycle time 92 60 ns min sclk cycle time ( r eadback mode) t 2 15 10 ns min sclk high time t 3 9 5 ns min sclk low time t 4 5 5 ns min sync to sclk falling edge setup time t 5 2 2 ns min sclk falling edge to sync rising edge hold time t 6 48 40 ns min minimum sync high time t 7 8 6 ns min sync rising edge to next sclk falling edge ignore t 8 9 7 ns min data setup time t 9 12 7 ns min data hold time t 10 13 10 ns min ldac falling edge to sync falling edge t 11 20 16 ns min sync rising edge to ldac falling edge t 12 14 11 ns min ldac puls e width low t 13 130 130 ns typ ldac falling edge to output response time t 1 4 130 130 ns typ sync rising edge to output response time ( ldac tied low) t 1 5 50 50 ns min clr pulse width low t 1 6 140 140 ns typ clr pulse activation time t 1 7 0 0 ns min sync falling edge to first sclk rising edge t 1 8 65 60 ns max sync rising edge to sdo tristate (c l = 50 pf) t 19 62 45 ns max sclk rising edge to sdo valid (c l = 50 pf) t 2 0 0 0 ns min sync rising edge to sclk rising edge ignore t 2 1 35 35 ns typ reset pulse width low t 2 2 150 150 ns typ r eset pulse activation time 1 all input signals are specified with t r = t f = 1 ns/v (10% to 90% of iov cc ) and timed from a voltage level of (v il + v ih )/2. 2 maximum sclk frequency is 35 mhz for write mode and 16 mh z for readback mode.
ad5781 data sheet rev. d | page 6 of 28 t 7 24 21 db23 db0 t 10 t 8 t 4 t 6 t 5 t 3 t 1 t 2 t 9 t 11 t 12 t 13 t 14 t 15 t 16 t 21 t 22 v out v out v out v out reset clr ldac sdin sync sclk 09092-002 figure 2. write mode timing diagram db23 db0 nop condition register contents clocked out t 1 t 17 t 2 t 5 t 17 t 5 t 19 t 18 t 20 t 3 t 4 t 8 t 9 t 6 t 7 24 2 2 1241 db23 db0 input word specifies register to be read sdo sdin sync sclk 09092-003 figure 3. readback mode timing diagram
data sheet ad5781 rev. d | page 7 of 28 absolute maximum rat ings t a = 25c, unless otherwise noted. transient currents of up to 100 ma do not cause scr latch - up . table 5 . parameter rating v dd to agnd ? 0.3 v to +34 v v ss to agnd ? 34 v to +0.3 v v dd to v ss ? 0.3 v to +34 v v cc to dgnd ? 0.3 v to +7 v iov cc to dgnd ? 0.3 v to v cc + 3 v or +7 v (whichever is less) digital inputs to dgnd ? 0.3 v to io v cc + 0.3 v or +7 v (whichever is less) v out to agnd ? 0.3 v to v dd + 0.3 v v refpf to agnd ? 0.3 v to v dd + 0.3 v v refps to agnd ? 0.3 v to v dd + 0.3 v v refnf to agnd v ss ? 0.3 v to +0.3 v v refns to agnd v ss ? 0.3 v t o +0.3 v dgnd to agnd ? 0.3 v to +0.3 v operating temperature range, t a industrial ? 40c to + 125c storage temperature range ? 65c to +150c maximum junction temperature, t j max 150c power dissipation (t j max ? t a )/ ja tssop package ja thermal impedance 143c/w jc thermal impedance 45c/w lead temperature jedec i ndustry s tandard soldering j - std -020 esd (human body model) 1.5 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a s tress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect dev ice reliability. this device is a high performance integrated circuit with an esd rating of 1.5 kv, and it is esd sensitive. proper precautions should be taken for handling and assembly. esd caution
ad5781 data sheet rev . d | page 8 of 28 pin configuration an d function descripti on 1 2 3 4 5 6 7 8 9 10 v out v refps v refpf clr reset v dd inv iov cc v cc ldac 20 19 18 17 16 15 14 13 12 1 1 agnd v ss v refns sync dgnd v refnf sdo sdin sclk r fb ad5781 t op view (not to scale) 09092-005 figure 4 . pin configuration table 6 . pin function descriptions pin no. mnemonic description 1 inv connection to inverting i nput of e xternal a mplifier. see the ad578 1 features section for further details . 2 v out analog o utput v oltage. 3 v refps positive r eference s ense v oltage i nput. a voltage range of 5 v to v dd ? 2.5 v can be connected. a unity gain amplifier must be connected at th is pin, in conjunction with the v refpf pin . see the ad5781 features section for further details. 4 v refpf positive r eference f orce v oltage i n put. a voltage range of 5 v to v dd ? 2.5 v can be connected. a unity gain amplifier must be connected at these pin, in conjunction with the v refps pin . see ad5781 features section for further details. 5 v dd positi ve a nalog s upply c onnection. a voltage range of 7 .5 v to 16.5 v can be connected. v dd should be decoupled to agnd. 6 reset active low reset logic input p in. asserting this pin return s the ad5781 to its power - on status. 7 clr active low clear logic input p in. asserting this pin sets the dac register to a user defined value ( s ee table 13 ) and updates the dac output. the output value depend s on the dac register coding that is being used, either binary or twos complement. 8 ldac active l ow load dac logic input pin. this is used to update the dac register and , consequently, the analog output. when tied permanently low, the output is updated on the rising e dge of sync . if ldac is held high during the write cycle, the input register is updated, but the output update is held off until the falling edge of ldac . the ldac pin should not be left unconnected. 9 v cc digital s upply c onnection. a voltage in the range of 2.7 v to 5.5 v can be connected. v cc should be decoupled to dgnd. 10 iov cc digital interface supply p in . digital threshold levels are referenced to the voltage applied to this pi n. a voltage range of 1.71 v to 5.5 v can be connected. iov cc should not be allowed to exceed v cc . 11 sdo serial d ata o utput p in. dat a is clocked out on the rising edge of the serial clock input. 12 sdin serial data input p in. this dev ice has a 24 - bit shift register. data is clocked into the register on the falling edge of the serial clock input. 13 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transfer red at clock rates of up to 3 5 mhz. 14 sync active low digital interface sy nchroniz ation input p in. this is the frame synchronization signal for the input data. when sync is low, it enables the input shift reg ister, and data is then transferred in on the falling edges of the following clocks. the input shift register is updated on the rising edge of sync . 15 dgnd ground r eference p in for d igital c ircuitry. 16 v refnf negative r eference f orce v oltage i nput. a voltage range of v ss + 2.5 v to 0 v can be connected. a unity gain ampl ifier must be connected at this pin, in conjunction with the v refns pin . see the ad5781 features section for further deta ils. 17 v refns negative r eference s ense v oltage i nput. a voltage range of v ss + 2.5 v to 0 v can be connected. a unity gain amplifier must be connected at these pin, in conjunction with the v refnf pin . see the ad57 81 features section for further details. 18 v ss negative a nalog s upply c onnection. a voltage range of ? 16.5 v to ? 2.5 v can be connected. v ss should be decoupled to agnd. 19 agnd ground reference pin for analog circuitry. 20 r fb feedback c onnection for e xternal a mplifier. see the ad5781 features section for furth er details .
data sheet ad5781 rev. d | page 9 of 28 typical performance characteristics 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 0 50000 100000 150000 200000 250000 dac code inl error (lsb) 09092-006 t a = +125c t a = +25c t a = ?40c ad8676 reference buffers ad8675 output buffer v refp = +10v v refn = ?10v v dd = +15v v ss = ?15v figure 5 . integral nonlinearity error vs. dac code, 10 v s pan 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 0 50000 100000 150000 200000 250000 dac code inl error (lsb) 09092-007 t a = +125c t a = +25c t a = ?40c v refp = +10v v refn = 0v v dd = +15v v ss = ?15v ad8676 reference buffers ad8675 output buffer figure 6 . integral nonlinearity error vs. dac code, +10 v s pan 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 0 50000 100000 150000 200000 250000 dac code inl error (lsb) 09092-008 t a = +125c t a = +25c t a = ?40c ad8676 reference buffers ad8675 output buffer v refp = +5v v refn = 0v v dd = +15v v ss = ?15v figure 7 . integral nonlinearity error vs. dac code, +5 v s pan 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 0 50000 100000 150000 200000 250000 dac code inl error (lsb) 09092-009 t a = +25c t a = ?40c t a = +125c ad8676 reference buffers ad8675 output buffer v refp = +10v v refn = 0v v dd = +15v v ss = ?15v figure 8 . integral nonlinearity error vs. dac code, 10 v s pan, x2 gain mode 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 0 50000 100000 150000 200000 250000 dac code dnl error (lsb) 09092-010 t a = +125c t a = +25c t a = ?40c ad8676 reference buffers ad8675 output buffer v refp = +10v v refn = ?10v v dd = +15v v ss = ?15v figure 9 . differential nonlinearity error vs. dac code, 10 v s pan 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 0 50000 100000 150000 200000 250000 dac code dnl error (lsb) 09092-011 t a = +125c t a = +25c t a = ?40c ad8676 reference buffers ad8675 output buffer v refp = +10v v refn = 0v v dd = +15v v ss = ?15v figure 10 . differential nonlinearity error vs. dac code, +10 v s pan
ad5781 data sheet rev . d | page 10 of 28 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 0 50000 100000 150000 200000 250000 dac code dnl error (lsb) 09092-012 t a = +125c t a = +25c t a = ?40c ad8676 reference buffers ad8675 output buffer v refp = +5v v refn = 0v v dd = +15v v ss = ?15v figure 11 . differential nonlinearity error vs. dac code, +5 v s pan 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 0 50000 100000 150000 200000 250000 dac code dnl error (lsb) 09092-013 t a = +25c t a = ?40c t a = +125c ad8676 reference buffers ad8675 output buffer v refp = +10v v refn = 0v v dd = +15v v ss = ?15v figure 12 . diffe rential nonlinearity error vs. dac code, 10 v s pan, x2 gain mode 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) inl error (lsb) 09092-014 10v s p an max in l +5v s p an max in l +10v s p an min in l +10v s p an max in l 10v s p an min in l +5v s p an min in l ad8676 reference buffers ad8675 output buffer v dd = +15v v ss = ?15v figure 13 . integral nonlinearity error vs. temperature 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) dnl error (lsb) 09092-015 10v s p an max dn l +5v s p an max dn l +10v s p an min dn l +10v s p an max dn l 10v s p an min dn l +5v s p an min dn l ad8676 reference buffers ad8675 output buffer v dd = +15v v ss = ?15v figure 14 . differential nonlinearity error vs. temperature 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 ?0.02 ?0.04 ?0.06 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 v dd /|v ss | (v) inl error (lsb) 09092-016 t a = 25c v refp = +10v v refn = ?10v ad8676 reference buffers ad8675 output buffer inl max inl min figure 15 . integral nonlinearity error vs. supply voltage, 10 v s pan 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 v dd (v) inl error (lsb) ?2.5 ?3.9 ?5.3 ?6.7 ?9.1 ?10.5 ?12.9 ?14.2 ?15.5 ?16.5 v ss (v) 09092-017 t a = 25c v refp = +5v v refn = 0v ad8676 reference buffers ad8675 output buffer inl max inl min figure 16 . integral nonlinearity error vs. supply voltage, +5 v s pan
data sheet ad5781 rev. d | page 11 of 28 0.08 0.06 0.04 0.02 0 ?0.02 ?0.04 ?0.06 ?0.08 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 v dd /|v ss | (v) dnl error (lsb) 09092-018 t a = 25c v refp = +10v v refn = ?10v ad8676 reference buffers ad8675 output buffer dnl max dnl min figure 17 . differential nonlinearity error vs. s upply voltage, 10 v s pan 0.10 0.05 0 ?0.15 ?0.10 ?0.05 ?0.20 ?0.25 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 v dd (v) dnl error (lsb) ?2.5 ?3.9 ?5.3 ?6.7 ?9.1 ?10.5 ?12.9 ?14.2 ?15.5 ?16.5 v ss (v) 09092-019 t a = 25c v refp = +5v v refn = 0v ad8676 reference buffers ad8675 output buffer dnl max dnl min figure 18 . differential nonlinearity error vs. supply voltage, +5 v s pan 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 v dd /|v ss | (v) zero-scale error (lsb) 09092-020 t a = 25c v refp = +10v v refn = ?10v ad8676 reference buffers ad8675 output buffer figure 19 . zero - scale error vs. supply voltage, 10 v span 0.14 0.12 0.10 0.04 0.06 0.08 0.02 0 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 v dd (v) zero-scale error (lsb) ?2.5 ?3.9 ?5.3 ?6.7 ?9.1 ?10.5 ?12.9 ?14.2 ?15.5 ?16.5 v ss (v) 09092-021 t a = 25c v refp = +5v v refn = 0v ad8676 reference buffers ad8675 output buffer figure 20 . zero - scale error vs. supply voltage, +5 v span 0.05 0.04 0.03 0.02 0.01 0 ?0.01 ?0.02 ?0.03 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 v dd /|v ss | (v) mid-scale error (lsb) 09092-022 t a = 25c v refp = +10v v refn = ?10v ad8676 reference buffers ad8675 output buffer figure 21 . midscale error vs . supply voltage, 10 v span 0.05 0 ?0.15 ?0.10 ?0.05 ?0.20 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 v dd (v) mid-scale error (lsb) ?2.5 ?3.9 ?5.3 ?6.7 ?9.1 ?10.5 ?12.9 ?14.2 ?15.5 ?16.5 v ss (v) 09092-023 t a = 25c v refp = +5v v refn = 0v ad8676 reference buffers ad8675 output buffer figure 22 . midscale error vs . supply voltage, +5 v span
ad5781 data sheet rev . d | page 12 of 28 ?0.015 ?0.020 ?0.025 ?0.030 ?0.035 ?0.040 ?0.045 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 v dd /|v ss | (v) full-scale error (lsb) 09092-024 t a = 25c v refp = +10v v refn = ?10v ad8676 reference buffers ad8675 output buffer figure 23 . full - scale error vs. supply voltage, 10 v span 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 ?0.01 ?0.02 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 v dd (v) full-scale error (lsb) ?2.5 ?3.9 ?5.3 ?6.7 ?9.1 ?10.5 ?12.9 ?14.2 ?15.5 ?16.5 v ss (v) 09092-025 t a = 25c v refp = +5v v refn = 0v ad8676 reference buffers ad8675 output buffer figure 24 . full - scale error vs. supply voltage, +5 v span ?0.30 ?0.35 ?0.40 ?0.45 ?0.50 ?0.55 ?0.60 ?0.65 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 v dd /|v ss | (v) gain error (ppm fsr) 09092-026 t a = 25c v refp = +10v v refn = ?10v ad8676 reference buffers ad8675 output buffer figure 25 . gain error vs. supply voltage, 10 v span 0.10 0.05 0 ?0.35 ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 ?0.40 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 v dd (v) gain error (ppm fsr) ?2.5 ?3.9 ?5.3 ?6.7 ?9.1 ?10.5 ?12.9 ?14.2 ?15.5 ?16.5 v ss (v) 09092-027 t a = 25c v refp = +5v v refn = 0v ad8676 reference buffers ad8675 output buffer figure 26 . gain error vs. supply voltage, +5 v span 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 v refp /|v refn | (v) inl error (lsb) 09092-028 t a = 25c v dd = +15v v ss = ?15v ad8676 reference buffers ad8675 output buffer inl max inl min figure 27 . integral nonlinearity error vs. reference voltage 0.10 0.05 0 ?0.05 ?0.10 ?0.15 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 v refp /|v refn | (v) dnl error (lsb) 09092-029 t a = 25c v dd = +15v v ss = ?15v ad8676 reference buffers ad8675 output buffer dnl max dnl min figure 28 . differential nonlinearity error vs. reference voltage
data sheet ad5781 rev. d | page 13 of 28 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 v refp /|v refn | (v) zero-scale error (lsb) 09092-030 t a = 25c v dd = +15v v ss = ?15v ad8676 reference buffers ad8675 output buffer figure 29 . zero - scale error vs. reference voltage 0.03 0.02 0.01 0 ?0.01 ?0.02 ?0.03 ?0.04 ?0.05 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 v refp /|v refn | (v) mid-scale error (lsb) 09092-031 t a = 25c v dd = +15v v ss = ?15v ad8676 reference buffers ad8675 output buffer figure 30 . midscale error vs. reference voltage 0.04 0.03 0.02 0.01 0 ?0.01 ?0.02 ?0.03 ?0.04 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 v refp /|v refn | (v) full-scale error (lsb) 09092-032 t a = 25c v dd = +15v v ss = ?15v ad8676 reference buffers ad8675 output buffer figure 31 . full - scale error vs. reference voltage ?0.30 ?0.35 ?0.40 ?0.45 ?0.50 ?0.55 ?0.60 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 v refp /|v refn | (v) gain error (ppm fsr) 09092-033 t a = 25c v dd = +15v v ss = ?15v ad8676 reference buffers ad8675 output buffer figure 32 . g ain error vs. reference voltage 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) full-scale error (lsb) 09092-034 10v s p an +10v s p an 5v s p an ad8676 reference buffers ad8675 output buffer v dd = +15v v ss = ?15v v refp = +10v v refn = ?15v figure 33 . full - scale error vs. temperature 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) mid-scale error (lsb) 09092-035 10v s p an +10v s p an 5v s p an ad8676 reference buffers ad8675 output buffer v dd = +15v v ss = ?15v v refp = +10v v refn = ?15v figure 34 . midscale error v s . temperature
ad5781 data sheet rev . d | page 14 of 28 1.2 1.0 0.8 0.6 0.4 0 0.2 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) zero-scale error (lsbs) 09092-036 ad8676 reference buffers ad8675 output buffer v dd = +15v v ss = ?15v v refp = +10v v refn = ?15v 10v s p an +10v s p an 5v s p an figure 35 . zero - scale error vs. temperature 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) gain error (ppm fsr) 09092-037 10v s p an +10v s p an +5v s p an ad8676 reference buffers ad8675 output buffer v dd = +15v v ss = ?15v v refp = +10v v refn = ?15v fi gure 36 . gain error vs. temperature 900 800 700 600 500 400 300 200 100 0 0 1 t a = 25c 2 3 4 5 6 logic input voltage (v) ioi cc (a) 09092-038 iov cc = 5 v , logic vo lt age increasing iov cc = 5 v , logic vo lt age decreasing iov cc = 3 v , logic vo lt age increasing iov cc = 3 v , logic vo lt age decreasing figure 37 . io i cc vs . logic input voltage 5 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 ?20 ?15 ?10 ?5 0 5 10 15 20 v dd , v ss (v) i dd , i ss (ma) 09092-039 t a = 25c i dd i ss figure 38 . power supply currents vs. power supply voltages 09092-040 ch3 5v ch4 5v 200ns 3 4 v dd = +15v v ss = ?15v v refp = +10v v refn = ?10v ad8676 reference buffers output unbuffered load = 10m?||20pf figure 39 . rising full - scale voltage step 09092-041 ch3 5v ch4 5v 200ns 3 4 v dd = +15v v ss = ?15v v refp = +10v v refn = ?10v ad8676 reference buffers output unbuffered load = 10m?||20pf figure 40 . falling full - scale voltage step
data sheet ad5781 rev. d | page 15 of 28 10.8 10.6 10.4 10.2 10.0 9.8 9.6 9.4 0 1 5 4 3 2 v out (mv) time ( s) 10v v ref output gain of 1 bias compens a tion mode 20pf compens a tion ca p aci t or rc low- p ass fi l ter 09092-063 figure 41 . 125 code step settling time 10 0 1 2 3 4 5 6 7 8 9 16384 65536 output glitch (nv?sec) code 114688 163840 212992 262144 311296 360448 409600 458752 507904 557056 606208 655360 704512 753664 802816 851968 901120 950272 999424 positive code change negative code change 5v output gain of 1 bias compens a tion mode 20pf compens a tion ca p aci t or rc low- p ass fi l ter 09092-059 v ref figure 42 . 6 msb segment glitch energy for 10 v v r ef 4.0 0 2.0 1.5 1.0 0.5 2.5 3.0 3.5 16384 65536 output glitch (nv?sec) code 114688 163840 212992 262144 311296 360448 409600 458752 507904 557056 606208 655360 704512 753664 802816 851968 901120 950272 999424 positive code change negative code change 10v v ref output gain of 1 bias compens a tion mode 20pf compens a tion ca p aci t or rc low- p ass fi l ter 09092-060 figure 43 . 6 msb segment glitch energy for 10 v v ref 3.0 ?0.2 2.2 1.0 1.4 1.8 0.6 0.2 2.6 16384 65536 output glitch (nv?sec) code 114688 163840 212992 262144 311296 360448 409600 458752 507904 557056 606208 655360 704512 753664 802816 851968 901120 950272 999424 negative code change 5v v ref output gain of 1 bias compens a tion mode 20pf compens a tion ca p aci t or rc low- p ass fi l ter positive code change 09092-061 figure 44 . 6 msb segment glitch energy for 5 v v ref 40 ?20 ?10 0 10 20 30 ?1.0 ?0.5 2.0 1.5 1.0 0.5 0 v out (mv) time ( s) 10v v ref output gain of 1 bias compens a tion mode 20pf compens a tion ca p aci t or rc low- p ass fi l ter c x = 143pf + 0pf c x = 143pf + 220pf c x = 143pf + 470pf c x = 143pf + 1,000pf 09092-062 figure 45 . midscale peak - to- peak glitch for 10 v 800 600 400 200 0 ?200 ?400 ?600 0 1 2 3 4 5 6 7 8 9 10 time (seconds) output voltage (nv) 09092-044 mid-scale code loaded output unbuffered ad8676 reference buffers t a = 25c v dd = +15v v ss = ?15v v refp = +10v v refn = ?10v figur e 46 . voltage output noise , 0.1 hz to 10 hz bandwidth
ad5781 data sheet rev . d | page 16 of 28 100 1 0.1 100k nsd (nv / hz) frequency (hz) 1 10 100 1k 10k 10 09092-064 v dd = +15v v ss = ?15v v refp = +10v v refn = ?10v code = midscale figure 47 . noise spectral density vs. frequency 350 300 250 200 150 100 50 0 ?50 0 1 ?1 2 3 4 5 6 time (s) output voltage (mv) 09092-049 t a = 25c v dd = +15v v ss = ?15v v refp = +10v v refn = ?10v ad8675 output buffer figure 48 . glitch impulse on removal of output clamp
data sheet ad5781 rev. d | page 17 of 28 terminolog y relative accuracy relative accuracy, or integral nonlinearity (inl), is a measure of the maximum deviation, in lsb, from a straight line passing through the endpoints of the dac transfer function. a typical inl error vs. code plot is shown in figure 5 . differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb max imum ensures monotonicity. this dac is guaranteed monotonic. a typical dnl error vs. code plot is shown in figure 9 . linearity error long - term stability linearity error long - term stability is a measure of the stability of the line arity of the dac over a long period of time. it is specified in lsb for a time period of 500 hours and 1000 hours at an elevated ambient temperature. zero - scale error zero - s cale error is a measure of the output error when zero - sc ale code (0x00000) is loade d to the dac register. ideally, the output voltage should be v refns . zero - scale error is expressed in lsbs. zero - scale error temperature coefficient zero - scale error temperature coefficient is a measure of the change in zero - scale error with a change in te mperature. it is expressed in ppm fsr/c. full - scale error full - scale error is a measure of the output error when full - scale code (0x3ffff) is loaded to the dac register. ideally, the output voltage should be v refps ? 1 lsb. full - scale error is expressed i n lsbs. full - scale error temperature coefficient full - s cale error temperature coefficient is a measure of the change in full - scale error with a change in temperature. it is expressed in ppm fsr/c. gain error gain error is a measure of the span error of th e dac. it is the deviation in slope of the dac transfer characteristic from ideal, expressed in ppm of the full - scale range. gain error temperature coefficient gain error temperature coefficient is a measure of the change in gain error with a change in tem perature. it is expressed in ppm fsr/c. midscale error midscale error is a measure of the output error when midscale code (0x20000) is loaded to the dac register. ideally, the output voltage should be (v refps C v refns )/2 +v refns . midscale error is express ed in lsbs. midscale error temperature coefficient midscale error temperature coefficient is a measure of the change in mid - scale error with a change in temperature. it is expressed in ppm fsr/c. output slew rate slew rate is a measure of the limitation in the rate of change of the output voltage. the slew rate of the ad5781 output voltage is determined by the capacitive load presented to the v out pin. the capacitive load in conjunction with the 3.4 k ? output impedance of the ad5781 set the slew rate. slew rate is measured from 10% to 90% of the output voltage change and is expressed in v/s. output voltage settling time output voltage settling time is the amount o f time it takes for the output voltage to settle to a specified level for a specified change in voltage. for fast settling applications, a high speed buffer amplifier is required to buffer the load from the 3.4 k? output impedance of the ad5781 , in which case , it is the amplifier that determines the settling time. digital -to - analog glitch impulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is specified as the area of the glitch in nv - s ec and is measured when the digital input code is changed by 1 lsb at the major carry transition (s ee figure 42). output enabled glitch impulse output e nabled glitch impulse is the impulse injected into the analog output when the clamp to ground on the dac output is removed. it is specified as the area of the glitch in nv - s ec (s ee figure 48). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac fro m the digital inputs of the dac but is measured when the dac output is not updated. it is specified in nv - s ec and measured with a full - scale code change on the data bus, that is, from all 0s to all 1s, and vice versa. spurious free dynamic range (sfdr) spurious free dynamic range is the usable dynamic range of a dac before spurious noise interferes or distorts the fu ndamental signal. it is measured by the difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full nyquist bandwidth (half th e dac sampling rate, or f s /2). sfdr is measured when the signal i s a digitally generated sine wave . total harmonic distortion (thd) tota l h armonic distortion is the ratio of the rms sum of the harmonics of the dac output to the fundamental value . only the second to fifth harmonics are included.
ad5781 data sheet rev . d | page 18 of 28 dc power supply rejectio n ratio. dc power supply rejection ratio is a measure of the rejection of the output voltage to dc changes in the power supplies applied to the dac. it is measured for a given dc change in power supply voltage and is expressed in v/v. ac power supply reje ction ratio (ac psrr) ac power supply rejection ratio is a measure of the rejection of the output voltage to ac changes in the power supplies applied to the dac. it is measured for a given amplitude and frequency change in power supply voltage and is expre ssed in d ecibels .
data sheet ad5781 rev. d | page 19 of 28 theory of operation the ad5781 is a high accuracy, fast settling, single, 18-bit, serial input, voltage output dac. it operates from a v dd supply voltage of 7.5 v to 16.5 v and a v ss supply of ?16.5 v to ?2.5 v. data is written to the ad5781 in a 24-bit word format via a 3-wire serial interface. the ad5781 incorporates a power-on reset circuit that ensures the dac output powers up to 0 v with the v out pin clamped to agnd through a ~6 k internal resistor. dac architecture the architecture of the ad5781 consists of two matched dac sections. a simplified circuit diagram is shown in figure 49. the six msbs of the 18-bit data-word are decoded to drive 63 switches, e0 to e62. each of these switches connects one of 63 matched resistors to either the v refp or v refn voltage. the remaining 12 bits of the data-word drive the s0 to s11 switches of a 12-bit voltage mode r-r ladder network. 2r s0 2r s1 2r s11 2r e62 2r e61 2r e0 12-bit r-r ladder ..................... ..................... .......... .......... rr r 2r v refpf v refps v refnf v refns v out six msbs decoded into 63 equal segments 09092-053 figure 49. dac ladder structure serial interface the ad5781 has a 3-wire serial interface ( sync , sclk, and sdin) that is compatible with spi, qspi, and microwire interface standards, as well as most dsps (see figure 2 for a timing diagram). input shift register the input shift register is 24 bits wide. data is loaded into the device msb first as a 24-bit word under the control of a serial clock input, sclk, which can operate at up to 35 mhz. the input register consists of a r/ w bit, three address bits, and twenty data bits as shown in table 7. the timing diagram for this operation is shown in figure 2. table 7. input shift register format msb lsb db23 db22 db21 db20 db19 db0 r/w register address register data table 8. decoding the input shift register r/ w register address description x 1 0 0 0 no operation (nop). used in readback operations. 0 0 0 1 write to the dac register. 0 0 1 0 write to the control register. 0 0 1 1 write to the clearcode register. 0 1 0 0 write to the software control register. 1 0 0 1 read from the dac register. 1 0 1 0 read from the control register. 1 0 1 1 read from the clearcode register. 1 x is dont care.
ad5781 data sheet rev . d | page 20 of 28 standalone operation the serial interface works with both a continuous and noncon - tinuous serial clock. a continuous sclk source can be used only if sync is held low for the correc t number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used, and sync must be taken high after the final clock to latch the data. the first falling edge of sync starts the write cycle. exactly 24 falling clock edges must be applied to sclk before sync is brought high again. if sync is brought high before the 24 th falling sclk edge, the data written is invalid. if more than 24 falling sclk edges are applied before sync is brought high, the input data is also invalid. the input shift register is updated on the rising edge of sync . for another serial transfer to take p lace, sync must be brought low again. after the end of the serial data transfer, data is automatically transferred from the input shift register to the addressed register. once the write cycle is complete, the output can be updated b y taking ldac low while sync is high. readback the contents of all the on - chip registers can be read back via the sdo pin. table 8 outlines how the registers are decoded. af ter a register has been addressed for a read , the next 24 clock cycles clock the data out on the sdo pin . t he clocks must be applied while sync is low. w hen sync is returned high , the sdo pin is placed in tris t ate . for a read of a single register, the nop function ca n be used to clock out the data. a lternatively , if more than one register is to be read, the data of the first register to be addressed can be clocked out at the same time the second register to be r ead is being addressed. the sdo pin must be enabled t o complete a readback operation. t he sdo pin is enabled by default. h ardware c ontrol p ins load dac function ( ldac ) after data has been transferred into the input register of the dac, there are two ways to update the dac register and dac output. depending on the status of both sync and ldac , one of two update modes is selected: synchronous dac updati ng or asynchronous dac updating. sync hronous dac update in this mode, ldac is held low while data is being clocked into the input shift register. the dac output is updated on the rising edge of sync . asynchronous dac update in this mode, ldac is held high while data is being clocked into the input shift register. the dac output is asynchronously updated by taking ldac low after sync has been taken high. the update now occurs on th e falling edge of ldac . reset function ( reset ) the ad5781 can be reset to its power - on state by two means : either by asserting the reset pin or by util i z ing the software reset control function ( s ee table 14 ). if the reset pin is not used, it should be hardwired to iov cc . asynchronous c lear function (clr) the clr pin is an activ e low clear that allows the output to be cleared to a user defined value. the 18 - bit clear code value is programmed to the c learcode register (see table 13 ). it is necessary to maintain clr low fo r a minimum amount of time to complete the operation (see figure 2 ). when the clr signal is returned high , the output remains at the clear value (if ldac is high) until a new value is loaded to the dac register. the output cannot be updated with a new value while the clr pin is low. a clear operation can also be performed by setting the clr bit in the software control register ( s ee table 14).
data sheet ad5781 rev. d | page 21 of 28 table 9 . hardware control pins truth table ldac clr reset function x 1 x 1 0 the ad5781 is in reset mode. t he device cannot be programmed. x 1 x 1 the ad5781 is returned to it s power - on state. al l registers are set to their default values. 0 0 1 the dac register is loaded with the clearcode register value , and the output is set accordingly. 0 1 1 the output is set according to the dac register value. 1 0 1 the dac register is loaded with the cl earcode register value , and the output is set accordingly. 1 1 the output is set according to the dac register value. 0 1 the output remains at the clear code value. 1 1 the output remains set according to the dac register value. 0 1 the output remains at the clear code value. 1 1 the dac register is loaded with the clearcode register value and the output is set accordingly. 0 1 the dac register is loaded with the clearcode register value and the output is set accordingly. 1 1 the outpu t remains at the clear code value . 0 1 the output is set according to the dac register value. 1 x is dont care. on - chip registers dac register table 10 outlines how data is written to and read from the dac register . table 10 . dac register msb lsb db23 db22 db21 db20 db19 db2 db1 db0 r/ w register a ddress dac r egister d ata r/ w 0 0 1 18- bits of d ata x 1 x 1 1 x is dont care. the follow ing equation describes the ide al transfer function of the dac: ( ) refn refn refp out v d v v v + ? ? = 1 2 18 w here: v refn is the negative voltage applied at the v refns input pin. v refp is the positive voltage applied at the v refps input pin. d is the 18 - b it c ode programmed to t he dac .
ad5781 data sheet rev . d | page 22 of 28 control register the control register controls the mode of operation of the ad5781 . table 11 . control register msb lsb db23 db22 db21 db20 db19.. .db11 db10 db9 db8 db7 db6 d b5 db4 db3 db2 db1 db0 r/ w register a ddress control r egister d ata r/ w 0 1 0 reserved reserved lin comp sdodis bin/2sc dactri opgnd rbuf reserved table 12 . control register functions clearcode register the c learcode register sets the value to which the dac output is set when the clr pin or clr bit is asserted. the output value depend s on the dac coding that is being used, either binary or twos complement. the d efault register value is 0 . table 13 . clearcode register msb lsb db23 db22 db21 db20 db19 db2 db1 db0 r/ w register a ddress clearcode r egister d ata r/ w 0 1 1 18- bits of d ata x 1 x 1 1 x is dont care. function description reserved these bits are reserved and should be pr ogrammed to zero. rbuf output amplifier configuration control . 0: i nternal amplifier, a1, is powered up and resistors rfb and r1 are connected in series as shown in figure 52 . this allows an external amplifier t o be connected in a gain of two configuration s . see the ad5781 features section for further details. 1: (default) i nternal amplifier, a1, is powered down and resistors rfb and r1 are connected in parallel as show n in figure 51 so that the resistance between the rfb and inv pins is 3.4 k?, equal to the resistance of the dac. this allows the rfb a nd inv pins to be used for input bias current compensation for an external unit y gain amplifier. see the ad5781 features section for further details. opgnd output ground clamp control. 0: dac output clamp to ground is removed , and the dac is placed in normal mode. 1: ( d efault) dac output is clamped to ground through a ~6 k? resistance, and the dac is placed in tristate mode. resetting the part puts the dac in opgnd mode, where the output ground clamp is enabled and the dac is tristated. setting the opgnd bit to 1 in the control register o verrules any write to the dactri bit dactri dac tri state control. 0: dac is in normal operating mode. 1: ( d efault) dac is in tristate mode. bin/2sc dac register coding select. 0: ( d efault) dac register uses twos complement coding. 1: dac registe r uses offset binary coding. sdodis sdo pin enable/disable control . 0: ( d efault) sdo pin is enabled. 1: sdo pin is disabled (tristate). lin comp linearity error compensation for varying reference input spans. see the ad5781 features section for further details . 0 0 0 0 (default) r eference input span up to 10 v. 1 1 0 0 reference input span of 20 v.
data sheet ad5781 rev. d | page 23 of 28 software control regis ter this is a write on ly register in which writing a 1 to a particular bit has the same effect as pulsing the corresponding pin low. table 14 . software control register msb lsb db23 db22 db21 db20 db19 db3 db2 db1 db0 r/ w register a ddress software c ontrol r egister d ata 0 1 0 0 reserved reset clr 1 ldac 2 1 the clr function has no effect if the ldac pin is low. 2 the ldac function has no effect if the clr pin is low. table 15 . software control register functions function description ldac setting this bit to 1 updates the dac register and cons equently the dac output. clr setting this bit to 1 sets the dac register to a user defined value (see table 13 ) and updates the dac output. the output value depends on the dac register coding that is being used, e ither binary or twos complement. reset setting this bit to 1 returns the ad5781 to its power - on state.
ad5781 data sheet rev. d | page 24 of 28 ad5781 features power-on to 0 v the ad5781 contains a power-on reset circuit that, as well as resetting all registers to their default values, controls the output voltage during power-up. upon power-on, the dac is placed in tristate (its reference inputs are disconnected), and its output is clamped to agnd through a ~6 k resistor. the dac remains in this state until programmed otherwise via the control register. this is a useful feature in applications where it is important to know the state of the dac output while it is in the process of powering up. configuring the ad5781 after power-on, the ad5781 must be configured to put it into normal operating mode before programming the output. to do this, the control register must be programmed. the dac is removed from tristate by clearing the dactri bit, and the output clamp is removed by clearing the opgnd bit. at this point, the output goes to v refn unless an alternative value is first programmed to the dac register. dac output state the dac output can be placed in one of three states, controlled by the dactri and opgnd bits of the control register, as shown in table 16. table 16. ad5781 output state truth table dactri opgnd output state 0 0 normal operating mode. 0 1 output is clamped via ~6 k to agnd. 1 0 output is in tristate. 1 1 output is clamped via ~6 k to agnd. linearity compensation the integral nonlinearity (inl) of the ad5781 can vary according to the applied reference voltage span; the lin comp bits of the control register can be programmed to compensate for this variation in inl. the specifications in this data sheet are obtained with lin comp = 0000 for reference spans up to and including 10 v and with lin comp = 1100 for a reference span of 20 v. the default value of the lin comp bits is 0000. output amplifier configuration there are a number of different ways that an output amplifier can be connected to the ad5781 , depending on the voltage references applied and the desired output voltage span. unity gain configuration figure 50 shows an output amplifier configured for unity gain, in this configuration the output spans from v refn to v refp. a1 6.8k ? 6.8k ? r1 r fb 18-bit dac v refps v refpf v refp v refn v refns ad5781 1/2 ad8676 ad8675, ada4898-1, ada4004-1 1/2 ad8676 v refnf r fb inv v out v out 09092-054 figure 50. output amplifier in unity gain configuration a second unity gain configuration for the output amplifier is one that removes an offset from the input bias currents of the amplifier. it does this by inserting a resistance in the feedback path of the amplifier that is equal to the output resistance of the dac. the dac output resistance is 3.4 k. by connecting r1 and r fb in parallel, a resistance equal to the dac resistance is available on-chip. because the resistors are all on one piece of silicon, they are temperature coefficient matched. to enable this mode of operation, the rbuf bit of the control register must be set to logic 1. figure 51 shows how the output amplifier is connected to the ad5781 . in this configuration, the output amplifier is in unity gain and the output spans from v refn to v refp . this unity gain configuration allows a capacitor to be placed in the amplifier feedback path to improve dynamic performance. 18-bit dac v refps 10pf v refpf v refp v refn v refns ad5781 1/2 ad8676 ad8675, ada4898-1, ada4004-1 1/2 ad8676 v refnf v out r fb r fb v out 09092-055 inv 6.8k ? 6.8k ? r1 figure 51. output amplifier in unity gain with amplifier input bias current compensation
data sheet ad5781 rev. d | page 25 of 28 gain of two configuration figure 52 shows an output amplifie r configured for a gain of two. t he gain is set by the internal matched 6.8 k ? resistors, which are exactly twice the dac resistance, having the effect of removing an offset from the input bias current of the external amplifier. in this configuration , the output spans from 2 v refn ? v refp to v r e f p. this configuration is used to generate a bipolar o utput span from a sin gle - ended reference input, with v refn = 0 v. for this mode of operation, the rbuf bit of the control register must be cleared to l ogic 0. a1 6.8k? 6.8k? r 1 r fb 18-bit dac v refps v refpf v ref p v refn = 0v v refns ad5781 1/2 ad8676 1/2 ad8676 v refnf r fb inv v out 09092-056 10pf ad8675, ada4898-1, ada4004-1 v out figure 52 . output amplifier i n gain of two config uration
ad5781 data sheet rev . d | page 26 of 28 applications information typical o perating c ircuit 09092-057 figure 53 . typical operating circuit figure 53 shows a typical operating circuit for the ad5781 using an ad8676 for reference buffers and an ad8675 as an output buffer. to meet the specified linearity, force se nse buffers must be used on the reference inputs. because the output impedance of the ad5781 is 3.4 k? , an output buffer is required for driving low re sistive, high capacitive loads. evaluation b oard an evaluation board is available for the ad5781 to aid designers in evaluating the high performance of the part with minimum effort. the ad5781 evaluation kit includes a populated and tested ad5781 pcb. the evaluation board interfaces to the usb port of a pc. software i s available with the evaluation board to allow the user to easily program the ad5781 . the software runs on any pc that has microsoft ? w indows ? xp (sp2) or vista (32 b it s ) installed. the eval - ad5781 data sheet is available, which gives full details on the operation of the evaluation board
data sheet ad5781 rev. d | page 27 of 28 outline dimensions compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarity 0.10 figure 54 . 20 - lead thin shrink small outline package [tssop] (ru - 20) dimensions shown in millimeters ordering guide model 1 temperature range inl package description package option AD5781BRUZ ? 40c to +125c 0.5 lsb 20- lead tssop ru -20 AD5781BRUZ - reel7 ? 40c to +125c 0.5 lsb 20- lead tssop ru -20 ad5781aruz ? 40c to +125c 4 lsb 20- lead tssop ru -20 ad5781aruz - reel7 ? 40c to +125c 4 lsb 20- lead tssop ru -20 eval - ad5781s d z evaluation boa rd 1 z = ro hs compliant part.
ad5781 data sheet rev . d | page 28 of 28 notes ? 2010 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09092 - 0- 7 /13(d)

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